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RRoma13's avatar
RRoma13
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4 years ago

system verilog signed'() extended sign bit wrong

module signed_test3( input logic clk, input logic [11:0] in, input logic [11:0] zero, output logic signed [15:0] d, output logic signed [15:0] d2 ); logic signed [15:0] c,c2; logic signed [...
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi RRoma13,


I'm unclear about your query. Could you kindly explain further?

Thanks


Regards,

Pavee




RRoma13's avatar
RRoma13
Icon for New Contributor rankNew Contributor
4 years ago

the apotheosis of this situation

module signed_test3(
input logic [11:0] a,
input logic [11:0] a1,
output logic [11:0]b,
output logic [11:0]b1
);

assign b[11:0] = unsigned'({a[11],a[10:0]});
assign b1[11:0] = unsigned'(a1[11:0]);

endmodule

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