Forum Discussion

RRoma13's avatar
RRoma13
Icon for New Contributor rankNew Contributor
4 years ago

system verilog signed'() extended sign bit wrong

module signed_test3( input logic clk, input logic [11:0] in, input logic [11:0] zero, output logic signed [15:0] d, output logic signed [15:0] d2 ); logic signed [15:0] c,c2; logic signed [...
RRoma13's avatar
RRoma13
Icon for New Contributor rankNew Contributor
4 years ago

if this module set as top level in quartus and run synthesis, then summator for signal c and c2 is different. for c2 is right. but for signal "c" is wrong. quartus reduce result of sum to one bit and connect this bit to all bits of register "c".(see picture of rtl viewer). like c[15:0]={{sum[0]}}.

and all simulators and Mentor Precision work normally, c and c2 is same.