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Ken_I_Intel's avatar
Ken_I_Intel
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7 years ago

System Verilog Pass typedef struct packed between modules Error (12002): Port "X" does not exist in macrofunction "Y"

Hi, I started to use typedef struct packed in my simulation no problems. However when I try to pass compile the and pass a struct it gives an error message. I just assumed I could pass a struct as...
jke's avatar
jke
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4 years ago

The issue still exists in Quartus version 20.1.0 and version 21.1.0.

I'm facing the same issue with my project. Very annoying!

I can reproduce this with the included project. Also the workaround seems to work, unfortunately not for my project.