System Verilog Pass typedef struct packed between modules Error (12002): Port "X" does not exist in macrofunction "Y"

Hi.,

Fyi I filed a support ticket already, but I probably was not specific enough in the forum. The way to generate this error is requires specific set of requirements. The error happens if:

• the project is setup in separate folder from the verilog source files
• AND the project settings to use Library path based search feature to find foo.sv rather than specify the file foo.sv in files setting
• AND all Quartus temporary files are deleted. (DB/INCREMENTAL_DB)

Attached is a zip with the entire demo project which will produce the error.

Once the error is occurs, it can be fixed by adding the file foo.sv to project. However the DB/INCRREMENTAL_DB/OUTPUT_FILES folders must be deleted otherwise the error continues. IE even if the fix is in place Quartus continues to fail.

So, Quartus must be closed, then it possible to delete ALL Quartus generated folders like DB/INCREMENTAL_DB/OUTPUTFILES, and then restart and recompile, it will compile without error.

Once it passed, the error condition can be put back into QSF by removing the foo.sv files and using the search path feature Quarys will continue to compile without any errors. But deleting the temp folder again, restarting quartus will then cuase the compile error to reoccur.

This issue was very annoying because it shows a conditional compile problem. As such I think Quartus needs a clean build / FULL REBUILD button like a c++ IDE would have because it clearly not doing a good job here.