System Verilog Pass typedef struct packed between modules Error (12002): Port "X" does not exist in macrofunction "Y"

​I compiled your same HDL coding without any issue in Quartus Standard version18.1. Also, I tried to duplicate the 2nd issue you had but not succeed. It could compile even the source file put at different place than its project directory.

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typedef struct packed

{

logic a;

logic b;

} t_ab;

endpackage

import types_package::*;

module foo (

input sys_clk,

input t_ab test_ab,

output foo_out

);

reg foo_out_r;

assign foo_out = foo_out_r;

always@(posedge sys_clk)

foo_out_r <= test_ab.a & test_ab.b;

endmodule

module struct_test (

input sys_clk,

input top_a,top_b,

output wire test_out

);

t_ab test;

assign test.a = top_a;

assign test.b = top_b;

foo foo1(

.sys_clk (sys_clk),

.test_ab(test),

.foo_out(test_out)

);

endmodule

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