System Verilog Pass typedef struct packed between modules Error (12002): Port "X" does not exist in macrofunction "Y"

Hi,

I think I found why I get 12002 error, and also I can pass structures as parameters in Quartus without having to hack my code back to array of wires. Quartus has bugs. There 1st issue is that once I see the error it remain even after making changes which will make it pass, I have to delete all temporary files and restart Quartus. The 2nd issue is that if the project uses sources files in a diffeent directory than the project files, quartus will generate the 12002 error if the library search feature is used. If every individual system verilog file is specified as a source files AND all the temporary files are deleted, then restarting Quartus will compile without error. Once it is passing, I can also revert the project settings to failing case and it will continue to pass.

I will escalate the issue as a Quartus BUG.