Sync and async clocks, fitter, ...

What you are ultimately talking about is crossing clock domains. When I design, I assume that all clocks are asynchronous to each other (unless the outputs are out of the same PLL). The fitter/timing analyzer will make moderate efforts to place registers crossing clock domains close together.

There are a few things you should keep in mind when designing:

1. Always register input signals (when possible) on the clock that you will be performing your work.

2. When sending single bits of data (pulses/flags), be sure to register them at least once before using them in your new clock.

3. Sending data buses can be a little tricky. Dual clock FIFOs are good at transferring data from one clock domain to another.

I might suggest attempting to work in one clock domain (with clock enables if needed) for the majority of your design and switching only at the edges of your design.