switching Bidirectional I/Os in FPGA

Well, I've used ModelSim and also the built-in simulator in Quartus II. Both show the same results, a high-Z value in the bidirectional data bus. What I'm trying to do is to switch the data bus from one processor to the other and also control the data flow on the data bus for the read and write transactions. Here's the code snippet"

assign fpga_sdram_d = (sdram_cs_n == 1'b0 && bf_swe_n == 1'b0) ? bf_data : {32{1'bz}};
assign bf_read_data = (sdram_cs_n == 1'b0 && bf_swe_n == 1'b1) ? fpga_sdram_d : {32{1'bz}};
assign fpga_sdram_d = (sdram_cs_n == 1'b1 && ts_sdwe_n == 1'b0) ? ts_data : {32{1'bz}};
assign ts_read_data = (sdram_cs_n == 1'b1 && ts_sdwe_n == 1'b1) ? fpga_sdram_d : {32{1'bz}};
assign bf_data = bf_read_data;
assign ts_data = ts_read_data;

Legends:

fpga_sdram_d - data bus (i/O) from FPGA to SDRAM (inout)

ts_data - Data bus from TS201 DSP to FPGA (inout)

bf_data - Data bus from BF561 to FPGA (inout)

ts_read_data - internal data signals for TS201

bf_read_data - internal data bus for BF561

As you can see, I'm trying to control the data bus direction for Read/Write based on the WE# and CS# signals. This is a simple code and should work. But in the simulations, always show the data bus (fpga_sdram_d) as High-Z.