switching Bidirectional I/Os in FPGA

Thanks. I've already checked out the Ref design at Altera. But thats got a custom interface with respect to the command bus. The controller gets its commands from the external processor and only decodes these commands into the SDRAM commands.

Now, if I have to use this in my design, I need to write the state machine for the commands b'coz the DSP processors dont have that command bus. I need to write the state machine for the Read/Write transactions based on the WR# and RD# signals from the processor. That's ok, but what bout the Burst transfers. How will the controller know if the transaction is burst read or burst write and issue the necessary commands?

I've also checked out the state machines that Google returns in the web search, but these state that they are the simplified ones. Anyways, returning the switching problem, in the code I've written a bidirectional buffer for the SDRAM data bus. This buffer is controlled by the chipselect and WE# signals to determine the data direction for a read or write.

In the testbench, I've driven the necessary SDRAM signals from the processor side and am switching these to the FPGA output that goes to the SDRAM chips. All the other control signals and address (RAS,CAS,CKE,etc) come out correctly. That is, they are switched from one of the processors selected and routed to the SDRAM chip. But the Data bus is always at an high-impedance 'Z' value. I've made sure that the test bench drives the waveforms correctly, the CS# and WE#. But still no go!