Hello,
With Vivado there is not problem to handle this situation:
The main RTL is synthesized in one vqm.
Then a small top level is synthesized with Synplify,
it instantiates the main level t...
I also got similar synthesis error in Vivado tool both version 2021.1 and 2022.2. Check image below.
The synthesis only can pass if the module name is different for example by changing either one to HV45_O25_CNHLSX4v2. Same thing goes for Quartus. Check image below.
Because if the module name is same but context of the modules are different , it'll be overwritten which caused the issue. If the module name is same and context of the modules are same as well then should be no problem even overwritten.