State Machine Viewer - missing transition

Hi Vikas,

thank you for the quick answer.

May be I didn't explain enough what I am doing

the two IFs are within a CASE within a PROCESS

So:

p_UART_RX : process(CLOCK)

begin

if rising_edge(CLOCK) then

case rx_state is

when...........................

--FIRST VARIANT

when s_rx_data_bits =>

if rx_clk_count < g_CLKS_PER_BIT-1 then

rx_clk_count <= rx_clk_count + 1;

rx_state <= s_rx_data_bits;

rx_smp_tick <= '0';

else

rx_clk_count <= 0;

rx_data <= rx_stable & rx_data(7 downto 1); -- LSB first

--rx_data(rx_bit_index) <= rx_stable; -- Wait g_CLKS_PEBIT-1 clock cycles to sample serial data

rx_smp_tick <= '1';

if rx_bit_index = 7 then -- !!!

rx_bit_index <= 0;

rx_state <= s_rx_stop_bit;

else

rx_bit_index <= rx_bit_index + 1;

rx_state <= s_rx_data_bits;

end if;

[/INDENT]

end if;[/INDENT]

--SECOND VARIANT

when s_rx_data_bits =>

if rx_clk_count < g_CLKS_PER_BIT-1 then

rx_clk_count <= rx_clk_count + 1;

rx_state <= s_rx_data_bits;

rx_smp_tick <= '0';

else

rx_clk_count <= 0;

rx_data <= rx_stable & rx_data(7 downto 1); -- LSB first

--rx_data(rx_bit_index) <= rx_stable; -- Wait g_CLKS_PEBIT-1 clock cycles to sample serial data

rx_smp_tick <= '1';

if rx_bit_index < 7 then --THE DIFFERENCE IS HERE

rx_bit_index <= rx_bit_index + 1;

rx_state <= s_rx_data_bits;

else

rx_bit_index <= 0;

rx_state <= s_rx_stop_bit;

end if;

[/INDENT]

end if;[/INDENT]

when...........................

when others => rx_state <= s_rx_idle;

[/INDENT]

end case;[/INDENT]

end if;

end process p_UART_RX;

THE both variant have the same behavior but in the state machine viewer the transition stroke are missing for the second, and I do not understand why?

Else the both code work correctly and a signal tab show correct transitions

Regards,

Emil