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Altera_Forum
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18 years ago

Specifying the latch edge for DDR output timing

This is a problem that I've had hanging over me for a while. I'm hoping someone can shed light on it. So, I need to implement some DDR output logic (not for memory, but just to send a high-spee...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

No, no, I'm still using both edges. The extra registers for the high phase data are clocked on the rising edge, and the extra registers for the low phase data are clocked on the falling edge.

In response to your email, the interface is source-synchronous and we do not have a PLL available for use with this clock.