Specifying the latch edge for DDR output timing

OK, I'm drawing out the timing you described and reviewing the timing commands available. I'll assume CycloneII family C8 when I compile. But first of all, if your problem is meeting timing with a large amout of combinatorial logic at the input of the IO element flip flop, you could perhaps add a pipeline stage flip flop and no longer have your timing quandry, as long as you can afford the extra clock of latency.