Occasional Contributor
Regular ContributorHi,
I feel you are not constraining both the interfaces. The AN 433 recommends to create virtual clock and the input clock for the same interface. Virtual clock to be used for input delay constraint whereas input clock to specify the other parameters. I think you are doing this for one interface only.
I am not seeing constraints for second interface. Once you define that, then you can define false paths between them, or alternatively set_max_delay will also do.
Regards.
Occasional ContributorSorry for the late response. Unfortunately this is not my only task.
The constraints i showed are only for one of the interfaces since they are independent of each other. Only the error is similar. My intention is to fix one of them to get an idea of what is going wrong. Everything else follows from this.
