Source Synchronous Interface - Hold Failure

Of course.

-0.3ns keep in account both the fact that data can goes out +/-50 ns and the fact that since clock has not 50% duty cycle, but only 45%-55%, means that if you look at edges the falling edge can be 250ps delayed or in advance from the point you expect it.

For the SETUP timing analisys, this difference in Duty Cycle it does not really matter since the latch edge is exactly the launch one delayed by 1.25ns by the PLL.

For the HOLD analisys things are different, since in this case the launch and latch clock are referring to two different edges and so if the following edge moves of 250ps in advance or in delay has to been considered.

I hope that now all is a bit less obscure :)

If you've some other doubts try to picture the waveform, they really help a lot.