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Altera_Forum
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14 years ago

Source Synchronous Interface - Hold Failure

Hi all, I've a design in which FPGA receive data in DDR with the clock (200MHz) and they are edge aligned. So FPGA shall shift clock 90° in order to capture data correctly and for that I've ins...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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set_input_delay -min -0.300 -clock virtual_ad_clk [get_ports AD_IN

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How do you get -0.3 as the min input delay? Could you explain a little about it?