Source Synchronous Centre Aligned DDR timing constraints don't work

First of all, you only need to use derive_pll_clocks once. Put it in the file after all your clock constraints. And don't use -use_net_name. You don't need it.

Next, for the PLL, I'm presuming you have it in source synchronous mode and the phase shift is set to 0 since you said you are doing center-aligned data.

For your 3rd and 4th set_input_delay constraints, those should be -clock_fall, not -fall. There's no option called -fall for clocks. That may be your main issue.

For your calculated input delay max and min, I am presuming you are using the skew method since you have positive and negative values for -max and -min, respectively. Verify that those values are correct.

Everything else looks ok.