Altera_Forum
Honored Contributor
18 years agoSOPC - simple question
Hi,
I am new here, so sorry for trivial questions:-) It's my first project in SOPC Builder (I use 5.1) and I'd like to add something very simple in order to learn how to use the tool. My VHDL code is simple counter from Altera site. But when I try to use Component editor, I see error: "slave must have a read or write interface, or support interrupts." I cannot add result signal. In signals tab there is only clock signal, which I set to type clk. I read tutorials, I finieshed it step by step but there was nothing about it. Here is code: LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY count IS PORT ( clock: IN STD_LOGIC; result: OUT integer RANGE 0 TO 31 ); END count; ARCHITECTURE rtl OF count IS SIGNAL result_reg : integer RANGE 0 TO 31; BEGIN PROCESS (clock) BEGIN IF (clock'event AND clock = '1') THEN result_reg <= result_reg + 1; END IF; END PROCESS; result <= result_reg; END rtl; Thank you for any help! Best regards, Koza