Forum Discussion
AndyRea
New Contributor
New Contributorsimulate parameterized ip block dcfifo_mixed_widths
using this as a verilog module included in a design inside a vhdl wrapper, how do i get modelsim to pick up the dcfifo_mixed_widths ip block properly so it can run testbenches?
// synopsys tran...
ShengN_altera
Super Contributor
Super ContributorHi,
What I can understand is you include the verilog module into VHDL wrapper. As for that, are you using VHDL for modelsim simulation?
Best regards,
Sheng
