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Altera_Forum's avatar
Altera_Forum
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13 years ago

Signaltap II and registered nodes

I have a register, declared as reg, that has various values added to it depending on the state of a state machine.

I would like to view it in SignalTap however it comes up as a combinational group as opposed to a register and therefore won't simulate. (Comes up highlighted red if I choose it).

Why is it a combinational group node and not a registered node?

I am using Quartus II V12.0 sp2. (Although I am editing files, without the project open, in V11.0 as there are horrible bugs in V12 that crash Quartus).

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Is it in a @posedge clk process? (In verilog, reg just means it's assigned in a process, but it could be a combinatorial process).

    I usually rely on the RTL Viewer to see how Quartus interprets the HDL, i.e. it should be a register, and if it is, then go to the Technology Viewer to try and figure out what the final logic looks like(although this is more difficult)
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    --- Quote Start ---

    Is it in a @posedge clk process? (In verilog, reg just means it's assigned in a process, but it could be a combinatorial process).

    --- Quote End ---

    It certainly is in a @posedge clk process.

    --- Quote Start ---

    I usually rely on the RTL Viewer to see how Quartus interprets the HDL, i.e. it should be a register, and if it is, then go to the Technology Viewer to try and figure out what the final logic looks like(although this is more difficult)

    --- Quote End ---

    OK.... thanks I will give this a try.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks... figured a workaround..... The RTL viewer was a help.

    The issue, I think, was that register was not doing anything and not really going anywhere so it was left out. (There for debug purposes).

    So outputting it to the real world solved my problems.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Open the Verilog in Quartus and go to:

    Edit -> Insert Template -> Verilog -> Synthesis Attributes

    The noprune one could help, i.e.:

    (* noprune *) reg regname;

    This way you don't have to bring them to a top-level.

    Also note that the synthesis report has some tables that help show why registers are removed. Sometimes just opening the .map.rpt and searching on the register name is the quickest.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    What I have found that works this best for actually seeing signals in SignalTap that are being optimized away is to use Quartus Synthesis --> Analysis and Elaboration only, then go into SignalTap and select your signal using the pre-synthesis filter, and then recompile. Your signal that is being optimized away will be retained and show up in SignalTap. This is a very useful subtle aspect of Quartus.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I'm thinking to create a small whitepaper on this and will post it to the wiki if I do.