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hcom's avatar
hcom
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Signal Tap example from Intel training course always fails timing

I was told to re-post this question because it didn't get resolved after 2 months: I am using Quartus Prime 21.1.0 Build 169 03/24/2021 SC Pro Edition to target a Cyclone 10 GX (10CX085) FPGA. I ...
  • Nurina's avatar
    Nurina
    4 years ago

    Hi,

    Thanks for bringing this up. This SDC constraints problem was probably missed by the internal team. I'll report this problem to them so they may rectify it.

    Regards,

    Nurina

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


We did not receive any response to the previous reply provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

Regards,

Nurina


P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution.