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FvM: I have seen discussions about this in other threads (Brad, Rysc, FvM and others) and i believe the conclusion was that very large routing delays would be inserted as long as the output flops were not in the output cell. I believe an example project was created where 20 ns was correctly inserted.
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Yes, I've noticed it. It's in deed a remarkable achievement of the Quartus II fitter. But to my opinion, it's far from a meaningful way to use timing constraints. I already made a remark regarding balanced timing. I think, the ideal balanced case is a design, that achieves the intended timing when all FPGA elements show their specified typical timing. Up to moderate clock frequencies, it wouldn't need timing constraints, cause the delay skew is below the available margin.
I understand, that this approach may be inapplicable for some designs. But this doesn't dispel my doubts about
unnatural timing constraints.
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