set_output_delay -min / -max does not have intended effect

You're source for the output generated clock seems to be a different name then the target of the PLL clocks. It still might work, just something I noticed. Everything will be related to the input clock, but since the data starts there and the clock going off chip starts there, they just cancel each other out. It's still correct that they start there.

(I've used reference_pin once, and though I got it to work, prefer putting a generated_clock on the output pin because it makes more sense to me and I have more control, since I've had cases where I needed to modify the clock constraint as it went off chip.)

Anyway, run the following:

report_timing -hold -detail full_path -npaths 10 -to [get_ports DATA_OUT*] -panel_name "h: data_out" -file "Data_Out_Hold.txt"

report_timing -setup -detail full_path -npaths 10 -to [get_ports DATA_OUT*] -panel_name "s: data_out" -file "Data_Out_setup.txt"

Then .zip up the two files and attach them. I'll get a much better sense of what's going on from that.