set_output_delay -min / -max does not have intended effect

Rysc:

I have changed my SDC but the clock to out delay does not change. I think the problem might be that the source synchronous clock is generated internally in the PLL while Quartus/TimeQuest appears to use the input clock to the PLL as reference. Since there is a path delay of 3.3ns from the input 48 MHz clock to the output 48MHz clock the timings appear to be some 3ns off (confirmed by my Logic Analyzer). The TimeQuest reports all show output delay min/max in relation to the input clock, not the output clock. This appears incorrect for a source-synchronous design?

Are PLL outputs phase locked to the PLL inputs? The reason i have a 48 MHz PLL output while the input clock is 48 MHz is that i'm generating a 48 MHz, 60 MHz and 120 MHz clock in the PLL and i want them all to be phase locked to each other. Since all clocks are phase locked i would get away with a single reset synchronization circuit for all three clocks.

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Very simple, the timing constraints can only achieve delays that are feasible within the given logic structure. The means to adjust the timing are very limited, mainly usage of different routing pathes and a rather small (around 0.5 ns maximum) additional output delay available with some FPGA families. I does neither cause structural changes, as moving registers from interal logic to output cells or vice versa nor adjust output drive strengths.

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FvM: I have seen discussions about this in other threads (Brad, Rysc, FvM and others) and i believe the conclusion was that very large routing delays would be inserted as long as the output flops were not in the output cell. I believe an example project was created where 20 ns was correctly inserted.

My latest SDC file is attached.

Thanks,

/John