set_output_delay -min / -max does not have intended effect

Very simple, the timing constraints can only achieve delays that are feasible within the given logic structure. The means to adjust the timing are very limited, mainly usage of different routing pathes and a rather small (around 0.5 ns maximum) additional output delay available with some FPGA families. I does neither cause structural changes, as moving registers from interal logic to output cells or vice versa nor adjust output drive strengths.

Above several ns delays usually can't be achieved by timing constraints without choosing an appropriate structure in advance respectively introducing structural changes manually. Another (probably better) way could be to use a phase shifted clock from a PLL.

Enabling physical synthesis may also help, but I would generally prefer a solution where the timing constraints are used to balance unavoidable routing delays rather than forcing a huge imbalance arbitrarily.