Set_input_delay misunderstanding

What if you're virtual clock is not the same frequency as the internal clock, or what if it has an offset? For example, if they're both 10ns clocks but the external clock is offset 2.5ns, then your setup relationship is 7.5ns and hold is -2.5ns. In this case, if we have positive slack on the paths, say 2ns, would we report the Fmax as 125MHz? Are we assuming the external clock also runs at 125MHz? Does it have a 2.5ns shift or a 90 degree shift? So in trivial cases Fmax can assume what the external clock does, but in non-trivial it can't. Rather than deciding to include cross-clock domain paths depending on how complicated they are, it's more straightforward to consider Fmax as only within a domain. In the end, I think Fmax should have never been reported, as it's trying to over-simplify something that is often more complicated. (And on the designs that really only have 1 domain, or no cross-domain paths, slack is not difficult to understand at all either, so Fmax isn't really simplifying much...)