Set_input_delay misunderstanding

Thank you for all the replies. I still need to digest the information..

Another question related to my example

Case 1

create_clock -period 20 [get_ports { RX_CLK }]

set_input_delay -clock { RX_CLK } -clock_fall -min $uC_tCOmin [get_ports { RC_Data0 }]

set_input_delay -clock { RX_CLK } -clock_fall -max $uC_tCOmax [get_ports { RC_Data0 }]

Adding this constrain removes the slack violation for hold time (shown in previous msg) using case 1 above but I am not quiet sure how these 2 constrains work together (even after reading the TQ guide)

|Data_out[31]} is the receiving FF of the shift register

set_min_delay -from [get_ports {RC_Data0 }] -to [get_registers {RCVR_Part|Data_out[31]}] -6

I want to clarify that the RC_Data0 is also an output to another pin of the FPGA (pin to pin -no logic) . The timing of the out pin is not critical at all. The important timing is the latching of RC_DAT0i to the first FF of the shifregister

Input pins to FPGA Internal logic

---->>RX_CLK -----------------------> shiftReg1_FF-clk

---->>RC_Data0-----------------------> shiftReg1_FF-Q

|

|

| Outpin of PFGA

|------------------>> RC_DAT0

thank you