Honored Contributor
Honored ContributorThe tCo timing was defined for the external device sending the data to the FPGA.
As indicated above, the results were different. a)Case1: In case the slack was -2.04 (fast-corner) Hold time: from RC_Data0 to FF of shiftregister slack from Node to node launch clk latch clk relation skew data delay -2.064 RC_Data0 Data_out[31] RX_CLK RX_CLK 0.000 1.758 2.276 B) Case2 . does not show any violation ( I am not sure how to get the same report to show what is the value of the path now) This is why I was wondering if I did something wrong as I used the same tCo-min and tC0-max for both cases and thank you
