Forum Discussion
Contributorseed -> how to get same SOF for each compilation run?
The source files drive the logic generation / mapping phases.
So if you compile with the exact same sources, the logic produced will be exactly the same.
The SEED value only drives the fitter.
Different SEED values will produce different placements of the exact same logic.
So if you don't change the source files, the logic will be the same.
If you don't change the seed, the placement will be the same.
Regular ContributorThe .fit.rpt file in your design directory lists what seed value was used for the design.
I have found that I can recompile over and over again, deleting all generated files and databases, and if I don't change any source files I end up with exactly the same FPGA .pof file. As indicated previously the .sof file my change as it has an embedded timestamp.
I don't know about displaying the timestamp in a .sof file, never tried to do that. The Windows maintained file date was sufficient for me.
Contributor1) I'm not using the POF files (they are manly for the MAX devices). For Cyclone 10 devices I'm using the JIC files, which are generated from the SOF files.
So, do the JIC files contain be the same timestamps as SOF? Will be the JIC files the same while using the same SEED.
2) As for the System Console, I'd wonder to know how I can check the timestamp if it's a part of JIC.
3) Anyway, I'd like to receive a response from an Intel's employee whether I'm guaranteed that the compiled logic be exactly the same when using the SAME SEED for the DIFFERENT COMPILATIONS. I mean exactly the same LOGIC used, SAME ROUTE and SAME TIMING REPORTS.
Thank you!
