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Honored Contributor
Honored ContributorSDC set_input_delay and set_output_delay constraints
Hello, I'm new to TimeQuest / SDC commands. In my design I've got an external Ethernet switch device that is sourcing a dedicated clock signal to drive data into an FPGA. The switch device al...
Altera_ForumHonored Contributor
Honored ContributorThat's quite the the thread resurrection...
From what I can now gather, kaz was describing the following situation: clk source (Ethernet chip) -> 2 ns -> FPGA -> 2 ns -> register (Ethernet chip) From the point of view of the Ethernet chip, this is see as if the data arrives 2+2 ns later relative to the clock edge, as seen by the Ethernet chip itself. Thus, the constraints should be: set_output_delay -max 14 set_output_delay -min 4
