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Altera_Forum's avatar
Altera_Forum
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14 years ago

rtl simulation problem for ddr3-high performance controller II

Hi,

When I simulated the given example in the External Memory Interface Handbook Volume 5 for ARRIA that I downloaded from .altera.com/support/examples/exm-list.jsp?cat=memory I found out this:

*1 local_ready signal is set only for 14 clock cycle during a 500 us simulation period. Does that make sense? Of-course not( the phy-clk is 150 MHz).

*2 next thing I did, I followed the tutorial in the same doc. The local_ready signal never set.

I haven't written any vhdl yet. I am only trying to simulate the given example *1 and a memory controller with example driver *2 which is generated by the mega-wizard.

Any similar experience or idea about what is happening.

Thanks

note : I am using free modelsim 10.0c and subscription edition of Quartus II 11.1

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hi,

    You just need to run the simulator much longer!

    The ready sets back after 1.3 ms.

    Good Luck!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hello, there were quite a few example design from the link provided, which one did you tried (perhaps the link has been updated)? I am trying the example for Arria V following altera.com/literature/hb/external-memory/emi_debug_verify.pdf, that ran OK. But I have trouble getting a different avalon port width to match my own design to simulate there...any experience in putting the controller in your own design? Thanks!