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Altera_Forum's avatar
Altera_Forum
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9 years ago

RTL sequence to VHDL translation

How would i place this RTL sequence and convert it into VHDL input:clk,mr,x,dat[6] output:rdy,err,resa[3].resb[3] registers;rega[3]. regb[3] sequence: 0. regb<=000 1. rega <=dat [5..3...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Hi there, I know alittle to get me through RTL to VHDL conversion.

The question i have is in regards to dat[6], is that written as data: In bit_vector (6 downto 0);

For resa[3] and resb [3], is it related in this form:

Architecture RTL_sequence to VHDL_translation is

Port (resa , resb: OUT_bit (3 downto 0);

or in

SIGNAL resa: bit_vector (3 downto 0);

resb: bit_vector (3 downto 0);