New ContributorHi everyone,
I registers are removed during synthesis and i used Intel P tile avalon MM PCI express & External Memory interface intel stratix 10 FPGA which are the registers are removed
Reasons are
1.Lost fan out
2. Struck at GND due to struck port data_in
how can i resolve it if anyone know please tell me
Thanks in advance
Regular ContributorWhy would you care if unused logic were removed during synthesis? It is NOT needed for the correct functioning of the design. Most design tools do this.
That being said, there are ways to prevent this if you really want to. In the case of registers:
reg reg1 /* synthesis preserve */;
works in verilog. It tells Quartus to preserve that register even if it is determined it is not needed.
New ContributorHi
Thanks for reply.
I need to get resource utilization of my design. I am using Intel P tile avalon MM PCIe Express and Intel PCIE 512 bit controller
need to accessing DDR memory for that i designed.
Warning(16735): Verilog HDL warning at intel_pcie_dma_hwtcl.sv(329): actual bit length 174 differs from formal bit length 160 for port "desc_rdata_o"
Warning(16735): Verilog HDL warning at inigo_pcie_intel_pcie_dma_0.v(64): actual bit length 32 differs from formal bit length 174 for port "dma_wrdm_tx_data_i"
because of this i am getting lost fan out
that's why i need to preserve these registers
Super ContributorThe resource usage reports in the Fitter folder of the Compilation Report will provide you with accurate resource counts, but if these are registers that you need that are getting optimized away, it would be better to try to figure out why they are being optimized away. If there are extra bits of a bus that are not connected to anything, they will get optimized away unless you preserve them as mentioned. You could also put Virtual Pin assignments on them to preserve them.
Super ContributorAnother way to prevent the register being remove is set design partition. Once the partition is set, those dangling register would not be optimized away.
New ContributorHi
Thanks for reply.
I need to get resource utilization of my design. I am using Intel P tile avalon MM PCIe Express and Intel PCIE 512 bit controller
need to accessing DDR memory for that i designed.
how can i do design partition?
thanks in advance
Super ContributorSince this thread had been answered, we shall close this thread. If you still need further assistance, you are welcome to post a response within 15days or open a new thread, some one will be right with you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
