Forum Discussion
SyafieqS
Super Contributor
2 years agoLet me know any update from previous reply
pharez
New Contributor
2 years agoThe design i tried was a simple AND gate using VHDL, i also tried using the block diagram and other gates, i set the simulator all the options and setting but when i create a new waveform simulation and get all the nodes in and try to simulate, the output continues to remain XXXXX and it doesn't report any errors