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Altera_Forum
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11 years ago

[Question about synchronous transfer] Will this kind of transfer cause problem?

I know for any asynchronous data transfers, we would need special handling mechanisms (i.e double sync, FIFO, handshaking, etc). I have a design that where the core logic interacts with the LVDS TX I...
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Altera_Forum
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11 years ago

This is still a synchronous system.

Why are you using two PLLs though? A single PLL with two output clocks, and a relative phase-shift between them would be more appropriate.

You can also dynamically phase-shift the PLL clocks. Using this you can sweep over the output data and determine what the optimal setup/hold time is for your system (and the amount of timing margin).

I posted controller code in this thread:

http://www.alteraforum.com/forum/showthread.php?t=46527

Cheers,

Dave