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Honored ContributorQuartus Warning(10631)
Hi all,
I received this warning during a compilation: warning (10631): vhdl process statement warning at serial_io_mux.vhd(79): inferring latch(es) for signal or variable "shift_registers_var", which holds its previous value in one or more paths through the process this is the process code: muxprocess : process(reset_i,clk_i,d_i)constant shift_reg_width : integer:=(input_num+output_num-1)/output_num;
-- serializzatori
type t_vector_array is array(output_num-1 downto 0) of std_logic_vector(shift_reg_width-1 downto 0);
variable shift_registers_var : t_vector_array;
variable bit_cnt_var : integer range 0 to shift_reg_width-1;
variable d_i_var : std_logic_vector((output_num*shift_reg_width)-1 downto 0);
variable sof_o_var : std_logic;
variable d_o_var : std_logic_vector(d_o'range);
begin
d_i_var:=(others=>'0');
d_i_var(d_i'range):=d_i;
if reset_i='1' then
bit_cnt_var:=0;
for i in 0 to output_num-1 loop
shift_registers_var(i):=d_i_var(((i+1)*shift_reg_width)-1 downto (i*shift_reg_width));
end loop;
sof_o_var:='0';
d_o_var:=(others=>'0');
elsif rising_edge(clk_i) then
if clk_int_en='1' then
if bit_cnt_var=0 then
bit_cnt_var:=shift_reg_width-1;
sof_o_var:='1';
for i in 0 to output_num-1 loop
shift_registers_var(i):=d_i_var(((i+1)*shift_reg_width)-1 downto (i*shift_reg_width));
end loop;
else
bit_cnt_var:=bit_cnt_var-1;
sof_o_var:='0';
end if;
for i in 0 to output_num-1 loop
d_o_var(i):=shift_registers_var(i)(0);
shift_registers_var(i)(shift_reg_width-2 downto 0):=shift_registers_var(i)(shift_reg_width-1 downto 1);
shift_registers_var(i)(shift_reg_width-1):='x';
end loop;
end if;
end if;
d_o<=d_o_var;
sof_o<=sof_o_var;
end process muxprocess; where am I going wrong?
