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TMayd's avatar
TMayd
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Quartus reporting unconstrained inputs and outputs on constrained paths

Hi I have implemented a set of timing constraints on my Arria 10 design and I'm confused about two things. [Running Quartus Pro 22.1] 1. Quartus is reporting one of my input clocks (it is a differ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hello,


It sounds like you are missing I/O constraints.

On Timing Analyzer, Report Unconstrained Paths and go to Setup/Hold Analysis>Unconstrained Input Ports.

This report should explain what's missing. Also, for the LVDS signal, I think the IP has generated SDC constraints so it doesn't appear as unconstrained input port. You can check Report SDC to see what constraints have been added.

You may find this training useful: https://www.youtube.com/watch?v=GItefNliYpM


Regarding the second question, I will have to investigate further and will update you on this soon.


Regards,

Nurina