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Altera_Forum's avatar
Altera_Forum
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18 years ago

Quartus puts in its own blocks

When I try writing a decoder circuit in Verilog, in the RTL viewer I see that Quartus has inserted its own block called "Decoder". A simple bitwise Exor is replaced by Add0, Add1 and so on. All...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Quartus knows the best implementations for common blocks (decoder, MUX ...). They will be separated from random logic for special treatment. So it recognized your decoder as a decoder. By the end of the line everything gets converted into FPGA cells. It is normal to see structures come and go as the circuit is processed.

Is there some reason you don't want it to recognize the decoder? People usually complain about NOT recognizing circuitry.