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4 years ago

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Quartus Pro 22.2 SystemVerilog: argument of size should be an identifier

.DATA_WIDTH ( $size({2'b0, 2'b0, 2'b0, 4'b0}) ) Quartus issues an error at Design Analysis Error(16845): Verilog HDL error at xxx.sv(270): argument of size should be an identifier It s...

ShengN_altera
4 years ago
Hi,

Check this https://www.intel.com/content/www/us/en/docs/programmable/683236/22-2/verilog-and-systemverilog-synthesis-support.html so latest SystemVerilog supported is SystemVerilog-2012. Then can refer to IEEE Standard 1800-2012 check here http://www.ece.uah.edu/~gaede/cpe526/2012%20System%20Verilog%20Language%20Reference%20Manual.pdf (page 604) under section 20.7 Array querying functions. You can see array_identifier is mentioned. There are some examples under that section as well for your reference.

This code can be synthesized in simulator. I tested in Questa Starter Edition with no problem. So means this is something supported in testbench. If so should be no problem too as testbench normally is not included in Quartus tool for compilation. Vivado 2021.2 still fails to synthesize $size but able to synthesize $bits. Check the images attached.

Thanks,

Best Regards,

Sheng

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Super Contributor

4 years ago

Sure. Thanks for your knowledge sharing. I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.