Forum Discussion
AdzimZM_Altera
Regular Contributor
4 years agoHi aegeus,
Can you unchecked and then check the default IO settings and generate the example design?
In the EMIF IP parameter (FPGA IO -> FPGA IO settings -> Use default IO settings)
Can test it for Agilex and Stratix 10 device?
Thanks.
Regards,
Adzim