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Have a thorough read through the
datasheet for the 'spi core' (
https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/qts/n2cpu_nii51011.pdf). This covers all aspects of the peripheral, what it should connect to, and how to control it.
You can also refer to the
spi slave to avalon master bridge design example (
https://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-spi-bridge.html) on Altera's website. This does everything you require.
Cheers,
Alex
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Alex,
I looked at the SPI slave to avalon master bridge design example, it looks like in Quartus 16.0 this example is demo for internal loopback?
If I want to use it as SPI master, I guess I have to link each pin using pin/chip planner to external interface?
Benson
Honored Contributor
