Honored Contributor
Honored ContributorI would like to understand this too. I think my problem is a little simpler, but shows similar quirky behavior of the tools when it comes to custom IP blocks.
In my project root directory I put my custom qsys IP in an "ip" directory. When I bring those components in, the _hw.tcl and verilog code exist within that directory. When I generate the Qsys system, sometimes my verilog code file is copied into the qsys_system_name/synthesis/submodules directory as it was when it was generated. Thus, when I edit the code in my ip directory, the changes do not get compiled when I build in quartus (it gets update if I regenerate). If I update the IP block in my ip directory, update the IP block to the new version in Qsys and generate, it creates a zero-size file of the same name in the synthesis/submodules directory -- but in this case if I rebuild the system with quartus, it will use the original source file for the compile. I briefly tried to force the paths based on some advice given by others but ultimately failed to get it to work -- maybe an answer to your questions will shed some light on the ones that I have seen. Lance
