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Altera_Forum
Honored Contributor
11 years agookk..The value of the signals will change only once the process ends. But i want the q and k value to change each timew it enters the j for loop..this is the code that needs to be modified so that k and q values are updated each time it enters the loop.
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ber is port ( clk : in std_logic ); end ber; architecture ar of ber is type data is array (0 to 11) of std_ulogic; signal d: data; -- give the input data bit by bit signal q:std_logic_vector(0 to 3):="0001"; signal k:std_logic_vector(0 to 3):="0000"; signal t: std_logic:='0'; begin p2: process(clk) variable count : integer := -1; begin if rising_edge(clk) then for j in 0 to 2 loop q<=(q(2)xor q(3)) &q(0)&q(1)&q(2); -- LFSR k<=q; end if; for t in 0 to 3 loop if (k(t) /= d(t+(4*j))) then count := count+1; end if; end loop; end loop; end process p2; end ar;