process inside another process?

Woooh !

1) I think you can't make a process inside a process

2) rename the loop variable 'j' and 't' OR rename/delete your SIGNALS 'j' and 't' : to avoid confusion

3) Could you post your schema ?

I bet you need a synchronous design, if so, employ

process(clk) -- or process(reset_n, clk) if you  had a reset_n
if rising_edge (clk) then
      q<=(q(2)xor q(3)) &q(0)&q(1)&q(2);
      k<=q;
   -- something like that : nested loops
   -- you must build finite loops because the FPGA have a finite number of logic elements AND synthesizer wouldn't want infinite structure.
   for j in 0 to 3 loop
      for t in 0 to 3 loop
         if (k(t) /= d(t+(4*(j-1)))) then
            count := count+1;
         end if;
      end loop;
   end loop;
end if;
end process;
-- It could be written easier, maybe.