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Altera_Forum
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17 years ago

Problems setting up LVDS on CycloneIII

Hi there, I'm trying to set up a 16x2 bit LVDS connection with a CycloneIII device. The actual model I'm using is the EP3C16Q240C8N. First, I'm verifying my config in the Quartus pin plann...
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Altera_Forum
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17 years ago

In addition, I don't know what a speed grade for Altera FPGA actually means. Most likely, there is a selection of wafers in production, but it's not excluded, that an individual -8 chip is capable of 840 MHz, so a prototype may operate. The fact that, -6 isn't available in PQFP (I wasn't aware of yet) possibly indicates reduced signal quality expectable with this package. This is known at least regarding ground bounce and SSO noise issues and is also reflected by some IO placement rules.

Good luck.