Honored Contributor
Honored ContributorSome properties are defined by Cyclone III hardware and can't be changed:
1. LVDS I/O needs VCCIO of 2.5V 2. Configuration interface is located in bank 1 3. -8 speed grade has maximum LVDS output data rate of 640 MHz Additionally, Altera doesn't supply AS configuration devices with supply voltage below 3.3V Also the manual suggests not to use level converters at AS interface and VCCIO level of 2.5V isn't specified to drive 3.3V IO-standards on output. As a result, your design can't work with LVDS in bank 1 if the other requirements have to be kept. Some conclusions: -To use 840 MHz LVDS with specified performance, you have to use -6 speed grade. -You must either move LVDS IO to another bank or find a way to use AS configuration with VCCIO of 2.5V. The most simple solution is to connect EPCS supply to 3.3V but operate the device in the 2.5V bank. To use AS configuration, it's not necessary to specify AS configuration in Quartus, only MSEL must be pin strapped correct, so you can specify VCCIO of 2.5 and connect an AS device anyway. Cause these method isn't supported by Altera officially, you have to verify correct operation on your own. -Other options would be: using level converters or EPCS compatible serial flash with 2.5V supply from other manufacturers
