Problem with SDRAM Timing

Note that the output of a PLL always drives a global. My guess is that your keep is basically telling it to keep that subsequent net, so it gets off that global and then probably gets back onto another global. So that's a really long delay being added to clock tree. To a certain degree, this counters the benefit of having a PLL. Plus, it's probably just luck that it happens to work. I would almost ignore that for now, and concentrate on your constraints.

Basically, you've constrained the internals but not the I/O ports, and therefore the SDRAM interface is not constrained. Are you sending a clock to the SDRAM, or is it a board level clock being used? Anyway, make sure you understand the I/O timing and start adding constraints.