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Is you DUT the ram? or is the DUT something else? If the DUT is not the ram, why not create a ram model that allows some other mechanism to initialise the ram contents, so you can just let the DUT have exclusive interface to the address interface?
Otherwise, what kind of ram is it? if it has integers as the addr interface, It must be a custom one of your own?
There are many solutions to this problem, but it really depends on the architecture.
Post some code/examples and maybe we can help in more detail.
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Thanks for your help!
The DUT consists of two modules a ram module and a discrete wavelet transform module, I want to test both and therefore I need to input the data into the RAM first. Yh it is a custom 2port ram, that can read while writing. Initializing the ram contents is a good idea, but I intend to add more modules that all operate on the same memory so that doesnt really solve my problem
entity true_dual_port_ram_single_clock is
generic
(
DATA_WIDTH : natural := 8;
ADDR_WIDTH : natural := 262144
);
port
(
clk : in std_logic;
addr_a: in natural range 0 to ADDR_WIDTH- 1;
addr_b: in natural range 0 to ADDR_WIDTH- 1;
data_a: in std_logic_vector((DATA_WIDTH-1) downto 0);
data_b: in std_logic_vector((DATA_WIDTH-1) downto 0);
we_a: in std_logic := '1';
we_b: in std_logic := '1';
q_a : out std_logic_vector((DATA_WIDTH -1) downto 0);
q_b : out std_logic_vector((DATA_WIDTH -1) downto 0)
);
end true_dual_port_ram_single_clock;
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