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Altera_Forum
Honored Contributor
9 years agoHi
Thanks for your efforts. @rsefton: Thanks for the link. I thought about changing the files manually before, but I really want to avoid this steps. Because they have to de done again and again every time I regenerate the system... So I hope there is an other solution. @ sstrell: As i see it right, there is nothing higher in the components hierarchy. Here is the generics part of the *.vhd. And I attached a picture of the parameters in the Component Editor and one where you can see how they are instantiatet in the Qsys System. library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library work; use work.SINC_pkg.all; ----------------------------------entity--------------------------------------------------- entity APB_SINC is generic ( MSB : integer := 16; OSR : integer := 100; CTRL : integer := 2; ORDER : integer := 3 ); port ( PCLK : in std_logic; PRESETn : in std_logic; PENABLE : in std_logic; PSEL : in std_logic; PADDR : in std_logic_vector(4 downto 0); PWRITE : in std_logic; PWDATA : in std_logic_vector(31 downto 0); PRDATA : out std_logic_vector(31 downto 0); PREADY : out std_logic; PSLVERR : out std_logic; IOMAESDATA : in std_logic; IOMEASCLK : in std_logic; IOMEASVALUE : out std_logic_vector(MSB-1 downto 0) ); end APB_SINC; https://www.alteraforum.com/forum/attachment.php?attachmentid=13255 https://www.alteraforum.com/forum/attachment.php?attachmentid=13256