Problem Assigning multibit output in SystemVerilog

Hello everyone!

I'm trying to set an multibit output with a state machine design in SystemVerilog. When I am running the testbench, I can see the inputs transitioning as expected but my output doesn't appear to be moving (I'm including a screenshot of what I'm seeing).

Basically, when state is S0, La should be 2'b10 and when state is S1, La should be 2'b01. Unfortunately, I don't know how to set more than a single bit using the assign command so I'm assigning each bit individually (which could be causing my issue). It's possible I should be using another command (or should be including it in a case statement) but I'm not sure where to go from here. Below is an excerpt of the code I am using:

module RandomModule(output logic  Lb);
typedef enum logic {S0, S1, S2, S3} statetype;
statetype state;
//More Code Here
//output logic
assign Lb=(state==S0);
assign Lb=(state==S1);
//More Code Here
endmodule

I would expect S0 to set Lb[1:0] to 0'b10 and S1 to set Lb[1:0] to 0'b01 but apparently, this is not the case. Can anyone help me with this? Thanks a lot!